NextRIPS support for forthcoming AMD processors

NextRIPS support for forthcoming AMD processors

Future versions of AMD processors will support a feature called
NextRIPS or Next RIP Save.  This feature causes the processor
to store the next sequential RIP of a guest in the VMCB on
most instruction interrupts.  The hypervisor can use this
information to determine how much memory to read to determine
the intercepted instruction, modestly improving performance.
The following patch implements support for this feature.

Signed-off-by: Mark Langsdorf <mark.langsdorf@amd.com>